1. Field of the Invention
The present invention relates to a test pattern for measuring an electric property in a semiconductor device and a test method using the test pattern, and more particularly, to a test pattern for measuring a contact resistance in a contact section and a test method using the test pattern.
2. Description of Related Art
Recently, the pattern size section in a semiconductor device becomes fine as progress of semiconductor technology. At the same time, the size of a contact hole also becomes fine. Further, an interlayer insulating film has been sufficiently planarized so that workability can be sufficiently accomplished. Conventionally, the interlayer insulating film had a hollow surface in a portion for a contact hole to have been formed. Accordingly, the depth of the contact hole was shallower by the hollow portion than the other portion of the interlayer insulating film. As described above, however, the planarization of surface is made to remove any hollow portion so that the depth of the contact hole becomes deep. As a result, since the plane size of the contact hole is also made fine, an aspect ratio of the contact hole increases abruptly. In the contact hole having such a great aspect ratio, there is typically employed a plug structure of contact in which electrically conductive material is filled in the contact hole in advance and which is covered by a metal layer, in order to prevent any break or disconnection between the conductive material and the metal layer. In this case, the contact resistance of the contact hole is composed of a plug resistance by the conductive material in the plug structure and an interfacial resistance between the conductive material and the metal layer.
When any failure is caused in the contact section, there is a case that it needs to be determined whether the cause is based on high plug resistance or high interfacial resistance. In this case, it is necessary to separately measure the plug resistance and the interfacial resistance. If the contact resistance is measured by use of a general method in the plug structure of contact, the sum of plug resistance and interfacial resistance, i.e., the contact resistance is measured. Thus, the plug resistance and interfacial resistance cannot be measured separately.
As a check pattern for separately measuring the plug resistance and the interfacial resistance is known a pattern disclosed in Japanese Laid Open Patent Disclosure (JP-A-Heisei5-129390). This check pattern is shown in FIG. 1. Referring to FIG. 1, the check pattern includes three electrode pad patterns 118, 119 and 120 formed on an interlayer insulating film. Four n-type semiconductor wiring patterns 117 and one n-type wiring pattern 115 which are formed under the interlayer insulating film are provided in series between the electrode pad patterns 118 and 119. Contact holes 116 are provided between the electrode pad pattern and the n-type wiring pattern and between the n-type wiring patterns such that the electrode pad patterns 118 and 119 are electrically connected. Similarly, four n-type semiconductor wiring patterns 114 and one n-type wiring pattern 115 which are formed under the interlayer insulating film are provided in series between the electrode pad patterns 119 and 120. The n-type wiring pattern 114 has the same width and depth as the wiring pattern 117 but the wiring pattern 114 is different from the wiring pattern 117 in length. Contact holes 116 all having the same size are provided between the electrode pad pattern and the n-type wiring patter and between the n-type wiring patterns such that the electrode pad patterns 119 and 120 are electrically connected.
In this check pattern, a first resistance and a second resistance are measured between the electrode pads 118 and 119 and between the electrode pads 119 and 120. As a result, a sheet resistance can be measured because the difference between the first and second resistances is based on the difference between the n-type semiconductor wiring patterns in length. Subsequently, using the resistance difference, the contact resistance can be determined precisely. In this conventional technique, however, the determined resistance is equal to the sum of the plug resistance and the interfacial resistance, i.e., the contact resistance in a case that contact has the plug structure and the plug resistance and interfacial resistance cannot be separately measured.
For this reason, a test pattern shown in FIG. 2 is tried in order to separately measure a plug resistance and an interfacial resistance. Referring to FIG. 2, the check pattern includes three electrode pad patterns 218, 219 and 220 formed on an interlayer insulating film. Five n-type semiconductor wiring patterns 217 having the same size and same resistance which are formed under the interlayer insulating film 222 are provided in, series between the electrode pad patterns 218 and 219. Contact holes 116 are provided between the electrode pad pattern 218 or 219 and the n-type wiring pattern 217 and between the n-type wiring patterns 217 such that the electrode pad patterns 118 and 119 are electrically connected. Similarly, five n-type semiconductor wiring patterns 217 which are formed under the interlayer insulating film 222 are provided in series between the electrode pad patterns 219 and 220. Contact holes 215 all having the same size are provided between the electrode pad pattern 219 or 220 and the n-type wiring pattern 217 and between the n-type wiring patterns 217 such that the electrode pad patterns 219 and 220 are electrically connected. In this case, the cross sectional views of the contact holes 216 and 215 when a semiconductor device is cut along lines 3A--3A and 3B--3B are shown in FIGS. 3A and 3B. As seen from the figures, the contact hole 216 has the same diameter as the contact hole 215 and the contact holes 216 and 215 are filled with the same conductive material. However, the contact hole 216 is different from the contact hole 215 in depth.
In this test pattern, a first resistance and a second resistance are measured between the electrode pads 218 and 219 and between the electrode pads 219 and 220. As a result, the difference of plug resistance between the contact holes 215 and 216 can be measured. Then, an interfacial resistance can be also determined using the determined plug resistance.
However, in the above conventional technique there is the following problem. That is, in order to make it possible to measure a resistance with probes, the dimension of test pattern is about 100.times.100 .mu.m. As a result, the measuring result contains an error due to ununiformity on a wafer surface.